Existing architectures for digital storage oscilloscopes (DSOs) and other test and measurement devices store acquired sample data within an acquisition memory, which is subsequently accessed by an acquisition rasterizer which produces waveform data suitable for use by a display raster memory associated with a display device. An example of such an architecture is depicted in U.S. Pat. No. 5,986,637 issued Nov. 16, 1999 to Etheridge et al. and incorporated herein by reference in its entirety.
These present architectures acquire data stored in an acquisition memory and, upon occurrence of a trigger event, the stored data is aligned to the triggering event and processed by an acquisition rasterizer. The resulting raster data is stored in a display raster memory for subsequent display on a display device.
Thus, the process of data acquisition must be complete prior to the process of rasterizing the acquired data. For long acquisitions, decimation is used to decrease the amount of data such that the data fits in available acquisition memory, which decimation inherently causes a loss of information. This loss of information has heretofore been deemed an acceptable tradeoff due to acquisition memory bandwidth limitations.